A block diagram of a conventional DLL (delay-locked loop) is shown in FIG. 1. A voltage controlled delay line consisting of differential delay elements 12, 14, . . . 16 takes an input clock signal refclk 10 and delays it by a precise amount based on its bias voltages 26, 28. When the DLL is locked to the reference clock, the delay of each delay element is Tclk/n, where Tclk is the clock period, and there are n differential delay elements 12, 14, . . . , 16. The delay line produces a delayed clock dclk 18. A feedback portion of the circuit compares the delayed clock dclk 18 to the reference clock refclk 10 and produces and adjusts the bias voltages Vnbias 26 and Vpbias 28 such that the delay is one clock period of the input clock. To do this, the feedback portion of the circuit has a phase detector 20 that compares the phase of refclk 10 to the phase of dclk 18. If the two are the same, the bias voltages should remain as they are. If the two are out of phase, the bias voltages should increase or decrease to speed up or slow down the delay line accordingly. The phase detector 20 produces digital up or down pulses whose duration is proportional to the phase difference detected. The up and down pulses are used by the charge pump 22 to adjust a control voltage Vctrl 23, typically stored on a loop filter capacitor. Vctrl is used by the biasing circuit 24 to set the bias voltages 26, 28.
A specific example of a differential delay element is shown in FIG. 2. The amount of delay introduced into a digital waveform passing through the delay element can be controlled with the analog bias voltages. The analog bias voltages change the trip points at which the delay element changes logical state. The delay elements use a differential structure in order to increase noise rejection. Input devices M2 42, M3 44 are a differential pair which steer output current through two branches. The analog voltage Vnbias on transistor M1 40 helps determine the delay through the delay element by controlling the total current through each branch. Devices M4 48, M5 50, M6 52, M7 54, make up two symmetric load elements 49, 51 that are used to provide a linear resistance load. Only load element 49 will be described in detail. The symmetric load 49 is made up of two PMOS devices 48, 50 connected in parallel. One device M5 50 has its gate tied to Vpbias while the other device M4 48 is diode connected. Vpbias also helps control the delay by determining the signal swing.
In order for the differential delay stage to operate properly, the bias voltages Vnbias, Vpbias must be set. These voltages are derived from another voltage, Vctrl 23 of FIG. 1. FIG. 3 shows an example of a conventional feedback circuit for generating the bias voltages Vpbias and Vnbias from Vctrl. Vctrl 23 is connected to an inverting input of an operational amplifier 102. The output of operational amplifier 102 is connected to the gate of transistor 104 and to the gate of transistor 114. A symmetric load 108 is connected to transistor 104 through additional transistor 106. The symmetric load 108 includes a first transistor 110 having its gate connected to a non-inverting input of the operational amplifier 102, and a second transistor 112 that is similarly connected. Transistors 114, 116, 111, 113 are connected in the same manner as transistors 104, 106, 110, 112, and operate as a buffer for the output. The bias voltages are indicated at Vpbias 28 and Vnbias 26.
The feedback circuit of FIG. 3 generates bias voltages that have the DC behaviour illustrated in FIG. 4. FIG. 4 shows a first curve 120 for Vctrl, a second curve 122 for Vpbias, and a third curve 124 for Vnbias.
Disadvantageously, the circuit of FIG. 3 includes significant complexity, in particular including operational amplifier 102 which in itself includes many transistors not shown in detail.